Processor performance and pipelining for OCR A-Level Computer Science: clock speed, cores and cache explained, with exam questions and a mark scheme. Processor performance and pipelining for OCR A-Level Computer Science: clock speed, cores and cache explained, with exam questions and a mark scheme. This free topic pack gives you everything for CPU Performance & Pipelining in one download: exam-style practice, the full answers to go with it, and a revision summary your students can keep. What’s included Question sheet - exam-style questions written to the OCR A-Level Computer Science (H446) specification, spec point 1.1.1. Mark scheme - complete answers with mark allocations, so students can self-assess and you can mark a full set in minutes. Revision cheat sheet - a condensed one-page summary of the key definitions, diagrams and facts for last-minute revision. What it covers Clock speed, and why raising it costs heat and power Number of cores, and why more cores are not always faster Cache size and the L1, L2 and L3 hierarchy How pipelining overlaps fetch, decode and execute Throughput versus single-instruction speed Exam focus The classic trap is claiming pipelining makes one instruction faster. It raises throughput. The mark scheme wants that distinction stated explicitly. How to use it Set the question sheet as homework, a lesson starter, a cover lesson or an end-of-topic assessment. Hand out the cheat sheet for revision or display it as a knowledge organiser. Because the mark scheme is included, students can mark their own work and see exactly where the marks are won and lost. Suitable for Year 12 and Year 13 students taking OCR A-Level Computer Science (H446), and teachers who want ready-made practice for spec point 1.1.1 without building it from scratch. Also useful for AS-level students and for anyone revising this topic independently. All three files are print-ready PDFs, so there is nothing to edit and nothing to set up. This resource was created by Shuttle Learning, a specialist in Computer Science education producing free Computer Science revision resources.

CPU architecture and the fetch-decode-execute cycle for OCR A-Level Computer Science: exam questions, full mark scheme and a revision cheat sheet. This free topic pack gives you everything for CPU Architecture & FDE Cycle in one download: exam-style practice, the full answers to go with it, and a revision summary your students can keep. What’s included Question sheet - exam-style questions written to the OCR A-Level Computer Science (H446) specification, spec point 1.1.1. Mark scheme - complete answers with mark allocations, so students can self-assess and you can mark a full set in minutes. Revision cheat sheet - a condensed one-page summary of the key definitions, diagrams and facts for last-minute revision. What it covers The Von Neumann architecture and its stored-program concept The ALU, control unit, registers and buses The PC, MAR, MDR, CIR and accumulator and what each holds Every stage of the fetch-decode-execute cycle in order Harvard architecture and how it differs from Von Neumann Exam focus Students routinely lose marks by naming registers without saying what they hold. The mark scheme rewards the full register-by-register walkthrough of the cycle. How to use it Set the question sheet as homework, a lesson starter, a cover lesson or an end-of-topic assessment. Hand out the cheat sheet for revision or display it as a knowledge organiser. Because the mark scheme is included, students can mark their own work and see exactly where the marks are won and lost. Suitable for Year 12 and Year 13 students taking OCR A-Level Computer Science (H446), and teachers who want ready-made practice for spec point 1.1.1 without building it from scratch. Also useful for AS-level students and for anyone revising this topic independently. All three files are print-ready PDFs, so there is nothing to edit and nothing to set up. This resource was created by Shuttle Learning, a specialist in Computer Science education producing free Computer Science revision resources.