pptx, 533.79 KB
pptx, 533.79 KB
This lesson works on the assumption that students have already been introduced to the Arithmetic Logic unit and section (a) of the 1.1.1 spec. This lesson covers: -

(b) – The fetch-decode-execute cycle, including its effect on registers.

(c) – The factors affecting the performance of the CPU, clock speed, number of cores, cache.

It includes some starter exam questions around the registers and answers are included in the presentation. Students will be expected to answer these questions. There is a research based task at the end which gets them to research other factors which have an impact on the CPU performance.

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